For the design of digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture.
One operation, which is often desirable in this process, is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as “floor planning.” A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks”, and then assigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
A typical integrated circuit is designed for implementation on a chip substrate. For example, a silicon substrate can have devices, such as standard cells, custom blocks, etc., formed on the substrate and interconnected by layers of metal which are separated by layers of dielectric materials.
A silicon chip dissipates power during operation. The temperature of the silicon chip rises while the heat generated from the power used by the circuit is being conducted away to the surrounding environment. The silicon substrate conducts away a portion of the heat, while the metal interconnect stack above the silicon substrate used for signal interconnect and power distribution conducts away a portion of the heat.
When the chip reaches a steady state for heat dissipation, at an elevated silicon temperature field equilibrium exists between the heat generated and the heat transported away by the temperature gradient created by the difference between the silicon temperature and the ambient temperature. The silicon temperature field is typically non-uniform. The temperature in the silicon chip typically varies according to the locations, depending on the local heat generation and the physical layout of the chip.
High temperature in an Integrated Circuit (IC) chip may reduce the reliability of the IC chip. Large temperature gradient in the chip may cause malfunction. For example, K. Banerjee, M. Pedram and A. H. Ajami (2001), “Analysis and optimization of thermal issues in high-performance VLSI,” Proc. of 2001 International Symposium on Physical Design (ISPD), provide an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability.
Some techniques have been developed to consider the steady state of the thermal conduction during the process of partitioning and placement. Examples of such techniques include: C. H. Tsai and S-M Kang (1999), “Standard Cell Placement for even on-chip thermal distribution,” Proc. of 1999 International Symposium on Physical Design (ISPD); Guoqiang Chen and Sachin Sapatnekar (2003), “Partition-Driven Standard Cell Thermal Placement,” Proc. of 2003 International Symposium on Physical Design (ISPD); Kyoung Keun Lee, Edward J. Paradise, Sung Kyu Lim (2003), “Thermal-driven Circuit partitioning and Floorplanning with Power Optimization,” Georgia Institute of Technology, Center for Experimental Research in Computer Systems, Technical Reports, GIT-CERCS-03-07. These techniques seek for an even temperature distribution in a partitioning and placement process during the early stage of a circuit design (e.g., floorplanning to breaking down a circuit design into blocks and lay out the blocks).
Some techniques for design optimization include three-dimensional integration. For example, S. Das, A. Chandrakasan and Rafael Reif (2004), “Timing, energy and thermal performance of three-dimensional integrated circuits,” Proc. of Great Lakes Symposium on VLSI (GL VLSI), show a method of combining multiple device layers with a high-density inter-layer interconnect for 3-D integration of a given circuit to provide better timing and energy performance relative to a single wafer implementation of the same circuit.